Communication and memory scheduling in reconfigurable image processing systems

The needs of highly complex computing architectures meanwhile do not only affect the computing elements itself, but also the communication between these elements: the design of a suited communication architecture for the transport of data streams with different characteristics such as data rates, data formats and real-time requirements using often shared physical channels is a great challenge and mandatory an integral task of the whole system design. In this PhD thesis, the design of an appropriate communication architecture will be explained by means of an advanced, FPGA-based PCI-Express-platform for the real-time processing of digital film data (minimum resolution 2048 x 1536 pixel, 283 MByte/s). As reference application the implementation of an algorithm for a wavelet-based noise reduction including motion estimation and -compensation is used. First, the encountered data streams are classified with respect to data rates, traffic patterns, real-time requirements and data formats, followed by an analysis of the physical transport channels and a presentation of the individual solutions for the data transport within FPGAs, between FPGAs, between several boards and between FPGAs and the external SDRAM memory. A main part of this thesis is the design and implementation of an optimizing DDR-SDRAM-controllers including support of different access patterns of processors and multiple stream-oriented data flows. First, different architecture evaluations are performed by means of SystemC models, and finally a freely configurable and synthezisable VHDL-implementation is presented. This part will be concluded by experiments using the target platform, which demonstrate the validity of the underlying architecture.