Predictable and runtime-adaptable network-on-chip for mixed-critical real-time systems

The industry of safety-critical and dependable embedded systems calls for even cheaper, high performance platforms that allow flexibility and an efficient verification of safety and real-time requirements. In this sense, flexibility denotes the ability to (online) adapt a system to changes (e. g. changing environment, application dynamics, errors) and the reuse-ability for different use cases. To cope with the increasing complexity of interconnected functions and to reduce the cost and power consumption of the system, multicore systems are used to efficiently integrate different processing units in the same chip. Networks-on-chip (NoCs), as a modular interconnect, are used as a promising solution for such multiprocessor systems on chip (MPSoCs), due to their scalability and performance. Hence, future NoC designs must face the aforementioned challenges. For safety-critical systems, a major goal is the avoidance of hazards. For this, safety-critical systems are qualified or even certified to prove the correctness of the functioning under all possible cases. A predictable behavior of the NoC can help to ease the qualification process (e. g. formal analysis) of the system. To achieve the required predictability, designers have two classes of solutions: isolation (quality of service (QoS) mechanisms) and (formal) analysis. For mixed-criticality systems, isolation and analysis approaches must be combined to efficiently achieve the desired predictability. Isolation techniques are used to bound interference between different application classes. And analysis can then be applied verifying the real-time applications and sufficient isolation properties. Traditional NoC analysis and architecture concepts tackle only a subpart of the challenges—they focus on either performance or predictability. Existing, predictable NoCs are deemed too expensive and inflexible to host a variety of applications with opposing constraints. And state-of-the-art analyses neglect certain platform properties (e. g. they assume sufficient buffer sizes to avoid backpressure) to verify the behaviour. Together this leads to a high over-provisioning of the hardware resources as well as adverse impacts on system performance (especially for the non safety-critical applications), and on the flexibility of the system. In this work we tackle these challenges and develop a predictable and runtime-adaptable NoC architecture that efficiently integrates mixed-critical applications with opposing constraints. Additionally, we present a modeling and analysis framework for NoCs that accounts for backpressure (i. e. full buffers in network routers delaying the progress of network packets). This framework enables to evaluate the performance and reliability early at design time. Hence, the designer can assess multiple design decisions and trade-offs (such as area, voltage, reliability, performance) by using abstract models and formal approaches.