Robustness and Usability in Modern Design Flows

Více o knize

The book addresses the challenges in designing and verifying increasingly complex integrated circuits. It analyzes current methodologies, identifies deficiencies, and proposes improvements in both design and verification processes. A comprehensive tool flow for Synthesis for Testability of SystemC descriptions is introduced, enabling fully testable circuits with efficient test pattern generation. Additionally, it presents a new paradigm for formal design verification, emphasizing design understanding and automated property generation, supported by empirical evaluations to enhance usability and robustness in design flows.