Formal Verification of Circuits

Více o knize

The book explores the critical role of formal verification in circuit design, particularly as designs grow increasingly complex with millions of transistors. It highlights the limitations of pure simulation and introduces innovative methods that leverage the regular structures of certain designs, such as ALUs. By utilizing Word-Level Decision Diagrams (WLDDs), which are graph-based representations, the book presents a more efficient way to verify functions with a Boolean range and integer domain, simplifying the verification process for complex circuits.