On application-specific network-on-chip synthesis and on-chip trace and debug

This work presents a complete methodology for the automatic synthesis of application-specific Network-on-Chip (NoC) topologies. The synthesized topologies are optimized according to the application running on the System-on-Chip (SoC). The developed algorithms can handle latency, port count, and link length constraints. They also support the generation of hybrid interconnects that utilize both shared buses and NoC routers. Additionally, this work presents an NoC architecture for non-intrusive trace and debug of SoCs. The architecture utilizes novel differential timestamps, which enable the construction of an accurate trace even in the presence of subsystem power down and frequency switching.