Performance Evaluation of Arithmetic Circuits Using GDI Full Adder

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Focusing on innovative logic designs, this work introduces two full adder cells that prioritize low power consumption and high speed through alternative internal structures. One design utilizes hybrid logic, while the other employs Gate Diffusion Input (GDI) to eliminate XOR/XNOR gates, enhancing efficiency. Both designs are tested with 180nm technology and demonstrate significant improvements in Power Delay Product (PDP), with simulations indicating an 80 percent advantage over traditional full adders. Comprehensive testing measures current and power supply performance.