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Design for Testability, Debug and Reliability

Next Generation Measures Using Formal Techniques

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Počet stran
188 stránek
Čas čtení
7 hodin

Více o knize

Focusing on the advancement of integrated circuits, this book presents innovative strategies for enhancing design testability, debugging, and reliability, particularly in safety-critical environments. It explores formal techniques like the Satisfiability (SAT) problem and Bounded Model Checking (BMC) to tackle challenges related to increasing test data volume and application time. Detailed evaluations of these methods are provided, alongside industry-relevant benchmarks, all within a unified framework that supports standardized software and hardware interfaces.

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Nákup knihy

Design for Testability, Debug and Reliability, Sebastian Huhn, Rolf Drechsler

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Rok vydání
2021
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