Knihu momentálně nemáme skladem

Více o knize
Focusing on advancements in integrated circuits, the book presents innovative strategies for enhancing design reliability and testability, particularly in safety-critical applications. It explores formal techniques like the Satisfiability (SAT) problem and Bounded Model Checking (BMC) to tackle challenges related to test data volume and application time. Detailed discussions and extensive evaluations of these methods are provided, alongside industry-relevant benchmarks. The authors integrate these approaches into a unified framework with standardized software and hardware interfaces.
Nákup knihy
Design for Testability, Debug and Reliability, Sebastian Huhn, Rolf Drechsler
- Jazyk
- Rok vydání
- 2022
- product-detail.submit-box.info.binding
- (měkká)
Jakmile ji vyčmucháme, pošleme vám e-mail.
Doručení
Platební metody
Navrhnout úpravu
- Titul
- Design for Testability, Debug and Reliability
- Podtitul
- Next Generation Measures Using Formal Techniques
- Jazyk
- anglicky
- Autoři
- Sebastian Huhn, Rolf Drechsler
- Vydavatel
- Springer International Publishing
- Rok vydání
- 2022
- Vazba
- měkká
- Počet stran
- 188
- ISBN13
- 9783030692117
- Kategorie
- Počítače, IT, programování
- Anotace
- Focusing on advancements in integrated circuits, the book presents innovative strategies for enhancing design reliability and testability, particularly in safety-critical applications. It explores formal techniques like the Satisfiability (SAT) problem and Bounded Model Checking (BMC) to tackle challenges related to test data volume and application time. Detailed discussions and extensive evaluations of these methods are provided, alongside industry-relevant benchmarks. The authors integrate these approaches into a unified framework with standardized software and hardware interfaces.