Design for Testability, Debug and Reliability

Více o knize

Focusing on advancements in integrated circuits, the book presents innovative strategies for enhancing design reliability and testability, particularly in safety-critical applications. It explores formal techniques like the Satisfiability (SAT) problem and Bounded Model Checking (BMC) to tackle challenges related to test data volume and application time. Detailed discussions and extensive evaluations of these methods are provided, alongside industry-relevant benchmarks. The authors integrate these approaches into a unified framework with standardized software and hardware interfaces.